Recent advances in the miniaturization of integrated circuits have led to smaller chip areas available for devices. High density dynamic random access memory chips (DRAMs), for example, leave little room for the storage node of a memory cell. Yet, the storage node (capacitor) must be able to store a certain minimum charge, determined by design and operational parameters, to ensure reliable operation of the memory cell. It is thus increasingly important that capacitors achieve a high stored charge per unit area.
Traditionally, capacitors integrated into memory cells have been patterned after the parallel plate capacitor. An interlayer dielectric material is deposited between the deposition of two conductive layers, which form the capacitor plates. Several techniques have recently been developed to increase the total charge capacity of the cell capacitor without significantly affecting the chip area occupied by the cell. These include the use of new high dielectric materials between the plates. Other techniques concentrate on increasing the effective surface area of the plates by creating folding structures, such as trench or stacked capacitors. Such structures better utilize the available chip area by creating three dimensional shapes to which the conductive plates and interlayer dielectric conform.
Stacked capacitors for memory cells may be formed within contact vias etched out of thick insulating layers over a semiconductor substrate 10. FIG. 1 illustrates a container capacitor 12 formed by such a method, as disclosed in U.S. Pat. No. 5,340,765, issued to Dennison et al. on Aug. 23, 1994. A first insulating layer 14 provides electrical isolation for underlying electronic devices such as thin film field effect transistors (FETs). Another insulating layer (not shown) is formed over the first insulating layer 14, and a via etched through the second insulating layer 14 may act as a template for the container capacitor. (FIG. 1 is a schematic cross-section which does not show the backwall of the container 12. In reality, the container resembles a three-dimensional cylinder.)
Via walls are lined with a conductive material 16, usually doped polycrystalline silicon (polysilicon). A planarizing etch is conducted to remove excess polysilicon over the top surface of the second insulating layer. The remaining second insulating layer may then be etched away to expose an outside surface 18 of the polysilicon container 12. The polysilicon walls 16 represent the bottom or storage electrode of the capacitor container 12. A thin dielectric layer 20 is then formed over both the outside and the inside of the polysilicon container walls, followed by a second conductive layer 22 (e.g., also polysilicon), which represents the top or reference electrode for the memory cell capacitor 12. By following the contours of the threedimensional container structure, the effective electrode surface area is substantially increased, allowing for substantially greater capacitance.
More complex structures, such as container-within-container or multiple pin structures, may even further increase electrode surface area and allow the extension of conventional fabrication materials to future generation memory devices. Fabrication of such structures, however, requires commensurately more complex processes, including multiple mask, deposition, and/or etch steps. Delicate container and multiple pin structures are extremely susceptible to breakage during inter-chamber transportation between these multiple process steps, which breakage could lead to shorting between the storage nodes of adjacent memory cells on a memory chip. Such shorting, in turn, tends to cause failure of an entire memory device. U.S. Patent No. 5,340,763, issued Aug. 23, 1994 to Dennison, discloses one method of forming multi-pin stacked capacitors while minimizing or containing the damage caused by such breakage.
Contact must also be made between the capacitor 12 and an underlying active area 25 of the semiconductor substrate 10. The contact must be formed between narrowly spaced transistor gates 28 (e.g., DRAM word lines), as shown in FIG. 1. Because the gates 28 of current memory cells are closer than 0.35 micron, and because the storage node should be as wide as possible to maximize electrode surface area, the contact is often formed by an etch mask separate from that which forms the contact via used to create the capacitor container 12. FIG. 1 illustrates a contact plug 30 formed by a separate mask prior to formation of the container structure. Combined with the multiple mask steps required of complex, multiple container or multiple pin capacitors, fabrication expense and risk of mask misalignment are increased.
A need therefore exists for a lower cost, reliable process for fabricating complex capacitor structures in integrated circuits. Ideally, such a process should minimize the number of mask steps required to create a high-surface area capacitor and form contact with underlying access devices.